University of California, Los Angeles - EC ENGR 115Cee115c_w14_disc_wk-5_extra-problem_Solution

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Electrical Engineering Department Winter 2014 1 EE115C: Discussion – Week 5 Solution Practice Problem 1 – CMOS Logic & Logical Effort (Previous Midterm Question) 1A Design ̅̅̅̅̅̅̅̅̅�... �̅̅̅̅̅ in Static CMOS. Draw the schematic and size all the transistors such that the worst-case delay is equal to that of a unit-sized inverter (WP:WN = 2:1). Solution: VDD Out A B C D D B C A 1 6 2 2 6 6 6 1 1B Find the logical effort for all the inputs in your design in part A? Solution: [Show More]

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