University of Texas, Dallas - CS 4141experiment-4. Familiarization with Sequential Logic Circuits (Flip-Flops)

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The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab Experiment #4 – Familiarization with Sequential Logic Circuits (Flip-Flops) 1. Introduction: In prev... ious laboratory exercises, we became familiar with logic gates which represented the six fundamental Boolean functions (NAND/AND, NOR/OR, XOR, and NOT) and the binary adder circuit. In this laboratory we will study another type of logic function namely sequential logic or flip-flop. Simple logic gates, such as we have studied so far, are referred to as combinational logic. Such logic circuits have outputs that depend only on their inputs. Thus, the output of a combinational logic circuit changes state as soon as the input stimulus is changed. Sequential logic circuits, on the other hand, may maintain their internal state, under certain conditions (and so long as power is available to the circuit) even when the input stimulus is changed. 2. Goal of this exercise: The purpose of Experiment #4 is to familiarize students with the functionality of the D and J-K flip-flops, and with the construction of a clocked flip-flop (essentially a clocked D-type FF). We will build the RS and clocked D flip-flop circuits in the lab. The purpose of Experiment is familiarize students with the functionality of the serial-to-parallel shift register and the simple binary counter. After operating the 74LS195 shift register and the 74LS163 binary counter, we will construct very similar devices from D and J-K flip-flops on our prototype boards. 3. Experimental Equipment List: The following experimental components are required for this experimental procedure: • IDL-800 Digital Lab. Circuits Evaluator (“breadboard” unit with test equipment and power supply built in) • IDL-800 User Manual (as required) • SN 74LS00 Quad NAND and 74LS04 Hex Inv. Dual In-Line packages (DIPs – digital logic kit) • SN 74LS74 D FF DIP (digital logic kit) • SN 74LS107 J-K FF DIP (digital logic kit) • Breadboard wire connection kit • Pin assignment diagrams for circuits noted above (see last page) 4. Pre-Work: Study some details on sequential logic circuits and flip-flops. Study the architecture and truth-table of D, RS and JK flip-flops. 5. Experimental Procedure: 1) D Flip-Flop: • Plug in the 74LS74 D-type flip-flop and connect ground to pin 7 and 5V to pin 14 as usual. This is a two-circuit DIP. Referring to the 74LS74 pin-out diagram, choose one of the two D FFs on the chip and connect the input switches to the D and Preset inputs. Since the preset is negative-true logic input, make sure the switch is set to 1. Connect the pulse switches (the negative-true outputs) to the Clock and Clear inputs. The Q and Q outputs should be connected to LED inputs. • Turn on the power. The D FF may power up in either state, so toggle the Clear pulse switch to initialize the circuit. After you do so, the Q LED should be off, and the Q LED on. Toggle the Preset switch (to low and back) and notice that the FF “sets” – that is, Q goes to 1 and its LED lights. The Preset switch allows an initial “on” state to be set before any clocked data is introduced into the FF, if the circuit requires an initial “on” condition. Toggle the Clear switch to reset the FF once more. [Show More]

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