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Consider the following control and datapath with datapath latencies in Table 1. Assume registers and data memory is edge-triggered and all hardware components can work concurrently when there are no ... data dependencies. To avoid being on the critical path, what is the maximum time to generate each of the following control signals: MemRead, ALUOp, MemWrite, ALUSrc, RegWrite? Given the control signal generation times in the following Table 2 and the datapath latencies in the above Table 1, derive the exact time to execute R-type, Load, and Store instructions Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline model Assume there is only one memory port, data forwarding is not implemented, and branch instruction stalls until the end of the WB stage. Complete the following pipeline execution diagram for one iteration. What is the CPI assuming there are infinite number of iterations? Assume structural hazards are resolved, data forwarding is implemented, and branch result is available at the end of the ID stage. Complete the following pipeline execution diagram for one iteration. What is the CPI assuming there are infinite number of iterations? Assume structural hazards are resolved, data forwarding is implemented, branch result is available at the end of the ID stage, and you may reorder the code to avoid pipeline stalls. Complete the following pipeline execution diagram for one iteration. What is the CPI assuming there are infinite number of iterations? Assume structural hazards are resolved, data forwarding is implemented, branch result is available at the end of the ID stage, loops are unrolled twice with unnecessary loop overhead eliminated, and you may reorder the code to avoid pipeline stalls. Complete the following pipeline execution diagram for one unrolled-iteration (i.e., two original iterations). What is the CPI assuming there are infinite number of iterations? Assume at most two instructions (i.e., one ALU/branch and one load/store) can be issued at each cycle, data access from/to memory does not interfere the instruction fetch, data forwarding is implemented, branch prediction is perfect (i.e., branch does not stall), and you may reorder the code within one iteration to avoid the pipeline stalls. Complete the execution diagram for one iteration. What is the CPI assuming there are infinite number of iterations? Assume at most two instructions (one ALU/branch and one load/store) can be issued at each cycle, data access from/to memory does not interfere the instruction fetch, data forwarding is implemented, branch prediction is perfect (i.e., branch does not stall), loops are unrolled four times with unnecessary loop overhead eliminated, and you may reorder the instructions to avoid the pipeline stalls. Complete the execution diagram for one unrolled-iteration (i.e., 4 original iterations). What is the CPI assuming there are infinite number of iterations? What optimizations will the gcc compiler perform on your code when you compile your code using the compilation flags “-O0”, “-O1”, “-O2”, and “-O3” respectively? Compile the C code we provided in your Assignment2-Answer with the compilation flags “-O0”, “-O1”, “-O2”, and “-O3” respectively and report the size (in bytes) of the executables produced by the three compilation approaches. Run the executables you get and compare the performance of different executables. Explain why the performance is different. [Show More]

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