University of California, Los Angeles - EC ENGR 115CEE Final-S11-Sol

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University of California, Los Angeles Henry Samueli School of Engineering and Applied Science Department of Electrical Engineering D. Markovic Mon Wed 8:00-9:50am Fri, Jun 10, 11:30am-2:30pm EE11... 5C: SPRING 2011—FINAL EXAM NAME Last First SID Please write answers in the box provided. Answers elsewhere will not be graded. Problem 1 _____/8 Problem 2 _____/30 Problem 3 _____/27 Problem 4 _____/15 Problem 5 _____/20 Total (100) You have 180 minutes. The test is designed so that you roughly spend 1.5 minutes per point + 30 minutes to check your answers. If you get stuck, move on. Good luck!EE115C: SPRING 2011—FINAL EXAM 2 PROBLEM 1: Logical Effort (10 pts) Assume the reference inverter for logical effort calculation has transistor width ratio Wp:Wn = 2:1. . Calculate logical effort g and parasitic delay p of the following logic gates. a. (2 pts) Sol: The NAND has equivalent pull-up and pull-down strength as the reference inverter. Thus, b. (2 pts) [Show More]

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